library ieee;
use ieee. std_logic_1164.all;
use ieee.numeric_std.all;

entity VGA_Ctrl is 
port(
  clk, rst : in std_logic;
  pix_en : in std_logic;
  HS, VS : out std_logic;
  pixel_x, pixel_y : out std_logic_vector(9 downto 0);
  last_column, last_row : out std_logic;
  blank : out std_logic
  );
end VGA_Ctrl;

architecture VGA_Ctrl_Arch of VGA_Ctrl is

-- pixel_x counter signals
signal pixel_x_reg : unsigned(9 downto 0);
signal pixel_x_inc : unsigned (9 downto 0);

-- pixel_y counter signals
signal pixel_y_reg : unsigned(9 downto 0);
signal pixel_y_inc : unsigned (9 downto 0);

--CONSTANT MAX : unsigned(9 downto 0) := 800;

signal HS_signal : std_logic;


begin
  
 
  
  -------------------------------------------
  --Counter for the Horizontal sync
  -------------------------------------------
  
  -- Register
  process(clk, rst)
    begin
      
      if (rst = '1') then
        pixel_x_reg <= (others => '0');
      elsif (clk'event and clk = '1') then
      if (pix_en = '1') then
        if (pixel_x_inc = to_unsigned(800, 10)) then
          pixel_x_reg <= (others => '0');
        else
        pixel_x_reg <= pixel_x_inc;
      end if;
      end if; 
      end if;
      
    end process;
    
    -- pixel_x next state logic
    
    pixel_x_inc <= pixel_x_reg + 1;
    
    -- output logic
    
    pixel_x <= std_logic_vector(pixel_x_reg);
    
    
    
    --------------------------------------------------
    -- HS and last column signal decoder
    --------------------------------------------------
    
     HS_signal <= '0' when (pixel_x_reg > to_unsigned(655, 10) and pixel_x_reg < to_unsigned(752, 10)) else
          '1';
          
   HS <= HS_signal;
    
    last_column <= '1' when (pixel_x_reg = to_unsigned(639,10)) else
          '0';      
    
    ---------------------------------------------------
    -- Vertical (Row) counter
    ---------------------------------------------------
     
    -- Register
  process(clk, rst)
    begin
      
      if (rst = '1') then
        pixel_y_reg <= (others => '0');
      elsif (clk'event and clk = '1') then
       if (pixel_x_reg = to_unsigned (657,10) and pix_en = '1') then
        if (pixel_y_inc = to_unsigned(521, 10)) then
          pixel_y_reg <= (others => '0');
        else
        pixel_y_reg <= pixel_y_inc;
      end if;
    end if;
      
      end if;
      
    end process;
    
    -- pixel_y next state logic
    
    pixel_y_inc <= pixel_y_reg + 1;
    
    -- output logic
    
    pixel_y <= std_logic_vector(pixel_y_reg);
    
    --------------------------------------------------
    -- VS and last row signal decoder
    --------------------------------------------------
    
    VS <= '0' when (pixel_y_reg > to_unsigned(489,10) and pixel_y_reg < to_unsigned(492,10))  else
          '1';
          
    last_row <= '1' when (pixel_y_reg = to_unsigned(479,10)) else
          '0';
        
    
    -- Blank signal output logic
    
    blank <= '1' when pixel_x_reg > 639 or pixel_y_reg > 479 else
            '0';  
  
  
  
  
end VGA_Ctrl_Arch;
  
  
   


